1. Field of the Invention
The present invention relates to a method of estimating wire length. More specifically, the present invention relates to a method of estimating wire length allowing highly precise estimation.
2. Description of the Background Art
In a semiconductor integrated circuit, wiring length becomes larger in inappropriately designed circuitry. In other words it takes more time for a signal to pass through the wiring, possibly resulting in a problem that the circuit operation cannot satisfy the required specification.
In view of the foregoing, in designing semiconductor integrated circuits, signal delay time is calculated based on the wiring length, when design of macro cell placement and wirings between macro cells (hereinafter referred to as "placement and wiring") is completed. Based on the calculated delay time, placement and wiring are modified to address inappropriate wiring.
However, modification of placement and wiring after completion of designing leads to large scale modification, and time necessary for modification is considerable. Accordingly, in order to minimize modification after placement and wiring, a wire length is estimated for each net in a semiconductor integrated circuit before placement and wiring. Further, placement and wiring are performed based on the estimated wire length. Here, the term "net" refers to wiring of macro cells.
Conventionally, the estimated wire length of each net has been based on the size of the area of placement to which the net belongs, and a out number of the net described below.
Referring to FIG. 1, the semiconductor integrated circuit includes a net 92 which is an object of estimation, a macro cell 90 connected to net 92 and a placement area 94 including net 92. The boundary length of placement area 94 including net 92 is represented by L, fan out number of net 92 is represented as F and constants determined based on design rule are represented by C1 and C2. The estimated wire length X of net 92 is calculated in accordance with the following equation (1), for example. EQU X=C1.times.L.times.F+C2 (1)
However, according to the conventional method, estimated wire length X of net 92 is calculated based only on the boundary length of placement area 94 including net 92 which is the object of estimation and on the number of fan out of the object net 92. Therefore, every net belonging to the same placement area 94 and having the same number of fan outs has the same estimated wire length. In an actual semiconductor integrated circuit, even when nets 92 belonging to the same placement area 94 have the same number of fan outs, the estimated wire lengths differ considerably dependent on the position of placement of macro cells 90 to which the nets 92 are connected, respectively. Therefore, for some nets 92, there is considerable difference between the actual wiring length and the estimated wire length, which makes highly precise placement and wiring difficult.